Experience of VHDL and/or Verilog programming languages
Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE)
Exposure to scripting language/s
Multi-FPGA design partitioning
Primary responsibilities will include
Design and coding using VHDL
FPGA simulation and verification
Lab-based analysis and debug on Hardware platforms
FPGA prototyping which may require partitioning the core on two or more FPGAs
Knowledge of PCI, PCI Express
Experience of Perl or C programming
Experience : 2-5 yrs
Qualifications : B.Tech / B.E.
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