Saturday, 9 June 2012

Specman Verification Engineer Jobs in Pune

VLSI - Verification

The Role

Primary responsibilities will include

§  Development of Verification Environment (VE) / Verification Component (VC) using Specman ‘e’ /system verilog

§  Writing tests, functional coverage using ‘e’ and mapping these to Verification plan

§  Functional verification of the design and achieve verification goals

§  VHDL / Verilog RTL/Testbench coding

Required Skills

§  An excellent knowledge of digital design / verification techniques

§  Minimum 2yrs experience with Specman / system verilog based verification for developing VE, VC, writing tests, functional coverage.

§  Experience of VHDL and/or Verilog programming languages.

§  Exposure to scripting language/s


§  2-5 yrs in the above mentioned areas.


Minimum B.Tech / B.E. with first class in electronic engineering or related stream.

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