Saturday, 7 April 2012

Verilog Jobs in Pune

The Role
    VHDL / Verilog RTL/Testbench coding
    Writing tests, functional coverage using ‘e’ and mapping these to Verification plan
    Functional verification of the design and achieve verification goals
    Development of Verification Environment (VE) / Verification Component (VC) using Specman ‘e’

Required Skills
    Minimum 2yrs experience with Specman based verification for developing VE, VC, writing tests, functional coverage.
    Experience of VHDL and/or Verilog programming languages.
    Exposure to scripting language/s

Thanks & Regards,
Somashekar .T.
Roland & Associates - Leaders in Social Media Recruitment.
Tel: 91-80-4282-1616 , 
Internet: ; ;

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