VHDL / Verilog RTL/Testbench coding
Writing tests, functional coverage using ‘e’ and mapping these to Verification plan
Functional verification of the design and achieve verification goals
Development of Verification Environment (VE) / Verification Component (VC) using Specman ‘e’
Minimum 2yrs experience with Specman based verification for developing VE, VC, writing tests, functional coverage.
Experience of VHDL and/or Verilog programming languages.
Exposure to scripting language/s