VLSI - VerificationThe Role
Development of Verification Environment (VE) / Verification Component (VC) using Specman ‘e’
Writing tests, functional coverage using ‘e’ and mapping these to Verification plan
Functional verification of the design and achieve verification goals
VHDL / Verilog RTL/Testbench codingRequired Skills
An excellent knowledge of digital design / verification techniques
Minimum 2yrs experience with Specman based verification for developing VE, VC, writing tests, functional coverage.
Experience of VHDL and/or Verilog programming languages.
Exposure to scripting language/sExperience : 2-5 yrs
Qualifications : B.Tech / B.E.
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Roland & Associates - Leaders in Social Media Recruitment.
Tel: 91-80-4282-1616 ,
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