Hiring :Specman / system verilog based verification Jobs in PuneThe Role
Primary responsibilities will include
Development of Verification Environment (VE) / Verification Component (VC) using Specman ‘e’ /system verilog
Writing tests, functional coverage using ‘e’ and mapping these to Verification plan
Functional verification of the design and achieve verification goals
VHDL / Verilog RTL/Testbench codingRequired Skills
An excellent knowledge of digital design / verification techniques
Minimum 2yrs experience with Specman / system verilog based verification for developing VE, VC, writing tests, functional coverage.
Experience of VHDL and/or Verilog programming languages.
Exposure to scripting language/sLocation : Pune
EXP : 2- 4 Years For immediate consideration, please send of your resume to firstname.lastname@example.orgSomashekar
Roland & Associates